1. Field of the Invention
The present invention relates to testing of I/O pins by utilizing an Alternating Current (AC) I/O loop back testing in a source synchronous mode.
2. Description of the Related Art
As the technology for manufacturing integrated circuits advances, more logic functions are included in a single integrated circuit device or a system on a chip (SoC). Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions. The fabrication of an IC incorporating such Very Large Scale Integration (VLSI) must be error free, as any manufacturing defect may prevent the IC from performing all of the functions that an IC or SoC is designed to perform. Such demands require verification of the design of the IC or SoC and also various types of electrical testing after the IC or SoC is manufactured.
However, as the complexity of the ICs and SoCs increase, so does the cost and complexity of verifying and electrically testing the individual IC or multiple ICs in a system for a SoC. Testing, manufacturing costs and design complexity increase dramatically because of the increasing number of functional pins on the integrated devices and SoC. With the increased number of I/O pins on each integrated device or system, the complexity and cost of testing each I/O pin has increased.
Verifying the functionality of an IC is typically accomplished by placing the IC on a tester that includes a tester channel for each I/O pin on the IC. Subsequently, each I/O buffer coupled to an I/O pin is tested for functionality, timing, performance, etc. However, there are often problems associated with testing an IC in this manner. One problem is that testing each I/O pin on an IC is time consuming and often expensive due to test equipment costs. Another problem is that the speed of the test equipment is typically not fast enough to keep pace with the IC. Moreover, existing test equipment is not capable of testing high-speed source synchronous systems.
In order to solve the problems of exclusively using a tester to test an IC, several contemporary testing schemes use the IC to assist in the testing. This process is commonly referred to as an I/O loopback test. I/O loopback tests are typically carried out by providing data from a functional logic block (or FLB) within the IC (e.g., a microprocessor), and driving the data out through the output component of each I/O buffer. Subsequently, the data is driven back through the input component of the I/O buffer to the FLB in order to verify if correct data has been received or not. Consequently, the IC verifies whether the input and output components of each I/O buffer is functioning properly.
The problem with conventional I/O loopback tests, however, is data is driven on a rising edge of a clock and strobe on a falling edge of the clock. Thus, the setup and hold margins are calculated based on the trailing edge of the data. As depicted in FIGS. 1 and 2, the loopback circuitry allows a strobe clock to be shifted (delayed) by one data clock cycle. Typically, the strobe and data pads can not use the same clock and are designed with excessive skew budget. Likewise, the delay lines consist of a large number of devices while each strobe clock utilizes their own delay line. Furthermore, in die variation from one delay line to another may cause measurement errors. Thus, present A/C I/O loopback testing that utilizes distributed delay pads results in inconsistencies due to large skew budgets, measurement errors and increased manufacturing cost since the strobe and data pads utilize different clock paths.